Digital Multiplier Architectures
In the realm of digital computing, the multiplier is one of the core functional units, performing a crucial task that underpins many complex computations. From image processing, and scientific computing, to neural network training, multipliers play a significant role, acting as the cornerstone of these applications. Today, we will delve into the intricate details of digital multiplier architectures, how they work, and how they are being refined to maximize performance.
Digital multipliers come in several architectures, each with its unique traits and application suitability. Let’s dig deeper into some of the most common ones:
- Array Multipliers: Recognized for their simplicity, array multipliers use an array of AND and full adder gates for generating and accumulating partial products. These multipliers’ straightforward design makes them easy to implement, although they may not offer the fastest computation time. The architecture of the array multiplier as explained in”Computer Organization” by Hamacher et. al is shown in Fig. 1.
- Wallace Tree Multipliers: Going beyond simplicity, Wallace Tree multipliers minimize the number of sequential adding stages, thereby speeding up the computation process. The generation of partial products, followed by their reduction into two binary numbers using carry-save adders, is the secret to their speed.
- Booth’s Multipliers: Known for their efficiency, Booth’s multipliers reduce the number of partial products by scrutinizing the multiplier operand bit by bit. Equipped with a powerful algorithm, Booth’s multipliers handle both positive and negative numbers efficiently, making them particularly useful for signed number multiplication.
References
- https://electronics.stackexchange.com/questions/593893/difficulty-in-understanding-the-analysis-of-worst-case-signal-propagation-delay
- Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer Organization, 2004, ISBN 0-07-112214-4
- https://vlsiverify.com/verilog/verilog-codes/wallace-tree-multiplier
- https://github.com/shubhi704/Booth-Algorithm/tree/main
Getting Started With Xilinx Petalinux
Xilinx Petalinux is a toolset that allows you to customize, build and deploy an embedded Linux application in a supported Xilinx FPGA like Zynp Ultrascale+ MPSoC. The toolset is available only for Linux, therefore if you are a Windows user consider installing Hyper-V or Virtual Box and creating a Ubuntu virtual machine.
Petalinux toolset contains the following tools to build custom embedded Linux images:
- Application, device driver and library generators and templates
- Bootable system image builder
- Debug agents
- GCC tools
- QEMU system simulator
Step 1: Build hardware description file
Linux communicates with the hardware using the technique called memory-mapped I\O. This requires a description of the addresses of each hardware IP (i.e. start address, address range). These details are passed on to Petalinux tools by means of a .xsa file (earlier known as .hdf file). The following tutorial describes in detail how to generate a .xsa file for a hardware design that contains only the processor system (PS).
The above tutorial contains only the PS. I added an additional processor reset block and keep the AXI HPM0 FPD and AXI HPM1 FPD (The abbreviation stands for advanced extensible interface high-performance master<number> full power) busses activated as shown below. These AXI masters are used to communicate with your custom hardware IPs.
In addition to the XSA file, you also need a board support package (BSP) to build a Linux image. The BSP is a collection of drivers customized to the hardware you are using. You can download the BSP from the below link if you are using a Xilinx board. Alternatively, you can generate your own as mentioned here.
Make sure the BSP you are downloading is the same version as your Petalinux tools version.
Step 2: Create Petalinux project
The Petalinux tools are accessible from the command line. Source the <Xilinx_Installation_Directory>/petalinux/settings.sh
The steps to build the Petalinux project and compile a simple hello world C application is provided below tutorial:
I also listed the commands that are required to create the Petalinux image below:
petalinux-create -t project -s <path to .bsp file> -n <project_name>
cd <project_name>
petalinux-config --get-hw-description=<path to .xsa file>
petalinux-build
cd images/linux
petalinux-package --boot --fsbl zynqmp_fsbl.elf --fpga <path to bitfile> --u-boot u-boot.elf
These steps will create the following files which need to be copied to the boot partition of the SD card. Once it is copied you can use that SD card to run Linux on your FPGA board
- BOOT.BIN
- u-boot.bin
- boot.scr
Connect to the serial port of the FPGA board using the following settings to verify that Linux is running properly:
Step 3: Create a Linux application
Open Vitis IDE and create a new platform project. This would require you to provide the previously generated .xsa file. Select the OS as Linux and the application processor you intend to use (i.e. psu_coretexa53 in ZCU104)
- Build the platform project using the hammer icon
- Create an application project : File->New->Application Project
- Select the platform we just created
- Follow the instructions for the application project:
- Select the platform we just created
- Give an application name : hello_linux
- Use the default domain : linux
- Keep SYSROOT, rootfs, and kernel image empty
- Select Linux Hello World template. Click Finish
- Click hammer icon to build the application project
Step 4: Running the program on FPGA
Debugging programs can be done using the debug mode. Use the Run As -> Run configurations to enable Single Application Debug. This allows stepping through the program lines to debug the application.
( To upload the application program to the FPGA you need to have a TFTP server installed in your machine. Instructions to install a TFTP server can be found here )
Conclusion
This short tutorial describes how to build an embedded Linux image using Petalinux tools and run a simple C application on the FPGA
Matlab: SoC Builder Xilinx RFSoC ZCU111 Example
This guide is written for Matlab R2021a and Vivado 2020.1
Matlab SoC Builder is an add-on that allows creating system on chip (SoC) design for a target device. An SoC design includes both hardware and software design which is generated with the help of HDL coder and Embedded coder toolboxes. Following toolboxes needs to be installed to start using Matlab SoC Builder.
Setting Up
Install the Matlab add-ons shown in Figure 1. Then open the “manage add-on” and click on the configure option of SoC Blockset Support Package for Xilinx Device. Follow the instructions to burn a bootable image to an SD card. Boot the RFSoC board with the SD card and test the connection. If the setup is successful the connection test will pass.
Step 1: Create a RFSoC project in Simulink
Step 2: Modify the example design [OPTIONAL]
Create Project in step 1 will generate an example design similar toFigure 3. The original example design uses the following configuration for the RF Data converter block
- RF Interface : ADC & DAC 1×1 interface
- Digital Interface : IQ
- Samples per clock cycle: 2
The default settings are changed to the settings shown in Figure 4. The settings are chosen to create a hardware loopback between filtered DAC output and ADC input using the XM500 balun board. The default samples per clock cycle settings are changed from 2 to 4 to further reduce the stream clock frequency.
After modifying the RF Data Converter IP, rewiring and model changes are required to build the system. The main changes are removing complex to real/imaginary converters and add bit concatenations to [0 15], [16 31], [32 47] and [48 63]. The source is a 500 kHz LUT-based sinusoidal signal generator. The original example uses two sources to generate the required 2 samples. In the modified design two additional sources are added with the correct phase offset to generate 4 samples in the same cycle.
NOTE: After applying the new settings stream data width gets changed to 64. However, if I close the window (After OK) and open it again the stream data width shows as 32. This seems like only an issue in displaying because the correct values are used for simulation and model compilation.
Open the Model Explorer and change the adc1Data type appropriately. In the above configuration it should change from uint32 to uint64.
Step 3: Configure and Build
The configure and build steps will ask you to review the task map and address map which you can auto map. This step will create a Vivado project and will run synthesis, implementation, and bit file generation. After the bit file is generated it can be loaded using the Load existing binaries option in Fig. 6. In Ubuntu, loading the binary has to be done after starting Matlab as the sudo user (This might be fixed in the future).
Simulating S-parameters from touchstone file (ADS)
RF vendors often provide S-parameter files (Touchstone format) for their components. These files can be used in ADS simulations to decide which component to use in your RF design. This tutorial explains how to import the touchstone file from the vendor website and generate the S-parameter plots.
Step 1: Download the S-parameter file
We will simulate the splitter from here which is MMIC power splitter operating in 1.7-3 GHz range.
Step 2: Import file to ADS
Open a new schematic in ADS and add N-Port S-Parameter file block from Data items. Use the browse option to select the downloaded touchstone file in the block properties.
Step 3: Add S-parameter simulation
Select the Simulation-S_parameters blocks and add SP block and 3 termG blocks. Connect the three “termG” blocks to the 3 ports of the splitter using wires. Change the start, stop and step frequencies to the operating frequency range of the device and then run the simulation.
Step 4: Add the measurments
The simulation results need to be shown in a rectangular plot which can be done as follows.
Summary
This simple example shows how to generate S-parameter plots from vendor-provided touchstones files in ADS. We used a 3-port power splitter in this example but the same method applies to N-port devices.
Launching My Personal Website
Hello there! If you are reading this post, chances are you are on my Facebook or LinkedIn profiles and know me well already. In that case, you might not find anything new on this website, but I still appreciate that you decided to have a peek. Please drop a comment if you have any suggestions to improve the site.
I decided to launch a personal website on May 23rd, 2020, when Facebook decided to block my profile out of the blue. I guess it was a mistake because they returned my profile the next day. But it got me thinking, how simple it is for Facebook to control what I have to say. So I started working on the website right away. Like my other projects, I only worked on this website on weekends, so it took me a month to get it ready.
I also wanted to give a special thanks to Kasun Sameera from my Synopsys gang, who took the only headshot of me, which looks good enough to put on the website. These photos are from 2017 in Manali, India. Also, a special shout-out to my pretty wife Hasantha, for pushing me to complete the site.
What's next? A lot of changes... The site needs more changes in both functionality and graphics. Also I'm planning to add tech articles on RF Systems, Signal Processing, and Electromagnetism. I already write lessons on chiphackers.com, which is my website focused on Digital Design and Computer Architecture. So tech articles on those fields will not be posted here.
That's about it. Thank you again for visiting. 🙂
Your time is limited, so don't waste it living someone else's life. Don't be trapped by dogma - which is living with the results of other people's thinking. Don't let the noise of others' opinions drown out your own inner voice. And most important, have the courage to follow your heart and intuition.