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Matlab: SoC Builder Xilinx RFSoC ZCU111 Example

This guide is written for Matlab R2021a and Vivado 2020.1

Matlab SoC Builder is an add-on that allows creating system on chip (SoC) design for a target device. An SoC design includes both hardware and software design which is generated with the help of HDL coder and Embedded coder toolboxes. Following toolboxes needs to be installed to start using Matlab SoC Builder.

Figure 1: Toolboxes related to Soc Builder

Setting Up

Install the Matlab add-ons shown in Figure 1. Then open the “manage add-on” and click on the configure option of SoC Blockset Support Package for Xilinx Device. Follow the instructions to burn a bootable image to an SD card. Boot the RFSoC board with the SD card and test the connection. If the setup is successful the connection test will pass.

Step 1: Create a RFSoC project in Simulink

Figure 2: Create new RF SoC project

Step 2: Modify the example design [OPTIONAL]

Create Project in step 1 will generate an example design similar toFigure 3. The original example design uses the following configuration for the RF Data converter block

  • RF Interface : ADC & DAC 1×1 interface
  • Digital Interface : IQ
  • Samples per clock cycle: 2
Figure 3: System diagram

The default settings are changed to the settings shown in Figure 4. The settings are chosen to create a hardware loopback between filtered DAC output and ADC input using the XM500 balun board. The default samples per clock cycle settings are changed from 2 to 4 to further reduce the stream clock frequency.

Figure 4: RF Data converter settings

After modifying the RF Data Converter IP, rewiring and model changes are required to build the system. The main changes are removing complex to real/imaginary converters and add bit concatenations to [0 15], [16 31], [32 47] and [48 63]. The source is a 500 kHz LUT-based sinusoidal signal generator. The original example uses two sources to generate the required 2 samples. In the modified design two additional sources are added with the correct phase offset to generate 4 samples in the same cycle.

NOTE: After applying the new settings stream data width gets changed to 64. However, if I close the window (After OK) and open it again the stream data width shows as 32. This seems like only an issue in displaying because the correct values are used for simulation and model compilation.

Open the Model Explorer and change the adc1Data type appropriately. In the above configuration it should change from uint32 to uint64.

Figure 5: Model explore which containing model parameters

Step 3: Configure and Build

Figure 6: Steps to configure and build the model

The configure and build steps will ask you to review the task map and address map which you can auto map. This step will create a Vivado project and will run synthesis, implementation, and bit file generation. After the bit file is generated it can be loaded using the Load existing binaries option in Fig. 6. In Ubuntu, loading the binary has to be done after starting Matlab as the sudo user (This might be fixed in the future).

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