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Digital Multiplier Architectures

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In the realm of digital computing, the multiplier is one of the core functional units, performing a crucial task that underpins many complex computations. From image processing, and scientific computing, to neural network training, multipliers play a significant role, acting as the cornerstone of these applications. Today, we will delve into the intricate details of digital multiplier architectures, how they work, and how they are being refined to maximize performance.

Digital multipliers come in several architectures, each with its unique traits and application suitability. Let’s dig deeper into some of the most common ones:

  • Array Multipliers: Recognized for their simplicity, array multipliers use an array of AND and full adder gates for generating and accumulating partial products. These multipliers’ straightforward design makes them easy to implement, although they may not offer the fastest computation time. The architecture of the array multiplier as explained in”Computer Organization” by Hamacher et. al is shown in Fig. 1.
Figure 1: Array multiplier architecture [2]
  • Wallace Tree Multipliers: Going beyond simplicity, Wallace Tree multipliers minimize the number of sequential adding stages, thereby speeding up the computation process. The generation of partial products, followed by their reduction into two binary numbers using carry-save adders, is the secret to their speed.
Figure 2: Wallace Tree Multiplier (source: https://vlsiverify.com/verilog/verilog-codes/wallace-tree-multiplier )
  • Booth’s Multipliers: Known for their efficiency, Booth’s multipliers reduce the number of partial products by scrutinizing the multiplier operand bit by bit. Equipped with a powerful algorithm, Booth’s multipliers handle both positive and negative numbers efficiently, making them particularly useful for signed number multiplication.
Figure 3: Flow chart of the booth multiplier algorithm (source: https://github.com/shubhi704/Booth-Algorithm/tree/main)

References

  1. https://electronics.stackexchange.com/questions/593893/difficulty-in-understanding-the-analysis-of-worst-case-signal-propagation-delay
  2. Carl Hamacher, Zvonko Vranesic, Safwat Zaky, Computer Organization, 2004, ISBN 0-07-112214-4
  3. https://vlsiverify.com/verilog/verilog-codes/wallace-tree-multiplier
  4. https://github.com/shubhi704/Booth-Algorithm/tree/main

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