100 Gbps Ethernet PCS IP
Description
Udara De Silva
December 10, 2015
The PCS (Physical Coding Subplayer) is responsible for performing frame and lane synchronization in IEEE 802.3 Ethernet standard. A PCS IP has been developed and verified using Xilinx VC709 FPGA board. A co-simulation architecture that uses MyHDL is introduced to verify functionality.