Ph.D. in Electrical Engineering2021 - Present Florida International University
In-band Full-Duplex, Digital Predistortion, Machine Learning
M.Sc. in Electrical Engineering2018 - 2021 Florida International University, USA
Real Time Systems and Applications, Advanced Microprocessor Systems, Advanced VLSI Systems
B.Sc. in Electronic and Telecommunication Engineering2011-2015 University of Moratuwa, Sri Lanka
Advanced Algorithms, Modular Software Development, Computer Organization, Communications
Research Assistant2018 - Present Florida International University
Research on machine learning accelerators and full duplex radios. Experience in using Xilinx RF SoC, Cadence Virtuoso and Matlab
Research Intern2021 Mitsubishi Electric Research Laboratories
Investigated the use of 1D convolution neural networks(CNN) in digital pre-distortion(DPD). A realtime 1D-CNN based DPD system is implemented and tested on FPGA.
Software Engineer2016 - 2018 Synopsys Inc.
As the primary developer of SDC parser in SpyGlass, worked on implementing new features using C/C++, Python, and Tcl,
Summer of Code2015 Google Inc.
In GSoC 2015, proposed to develop a SDRAM controller using a Python high-level synthesis tool called MyHDL. SDRAM controller was verified in XuLA2-LX25 FPGA board
RTL Design (Verilog)
RF System Design
Digital Signal Processing
Data Structures and Algorithm Design
Embedded Programming (Linux)
Udara is a very talented Engineer who worked with me around one and half years in Synopsys. He has eager to learn new things. He is one of the best employees that I have ever worked. Because, I could hand over one of my complete project ownership to him, even when he was newly joined Synopsys as fresh graduate. He did excellent job in that role. He maintained that project as an experienced guy. Udara is a great guy to work with.
Awards & Achievements
Bronze MedalMath Olympiad
Winner (2 nd place)MangoHacks 2019
Bronze MedalPhysics Olympiad
Winner (Sponsor Award)ShellHacks 2019
Ranked 9 (Colombo) 23 (Island)G.C.E A/L
Most Outstanding StudentD.S. Senanayake College
- A broadband multistage self-interference canceller for full-duplex MIMO radios H. Zhao et al., "A Broadband Multistage Self-Interference Canceller for Full-Duplex MIMO Radios," in IEEE Transactions on Microwave Theory and Techniques, vol. 69, no. 4, pp. 2253-2266, April 2021, doi: 10.1109/TMTT.2021.3060792.
- A direct-conversion digital beamforming array receiver with 800 MHz channel bandwidth at 28 GHz using Xilinx RF SoC S. Pulipati et al., "A Direct-Conversion Digital Beamforming Array Receiver with 800 MHz Channel Bandwidth at 28 GHz using Xilinx RF SoC," 2019 IEEE International Conference on Microwaves, Antennas, Communications and Electronic Systems (COMCAS), 2019, pp. 1-5, doi: 10.1109/COMCAS44984.2019.8958039.
- Design of 28 GHz 64-QAM digital receiver S. Pulipati, V. Ariyarathna, U. De Silva, N. Akram, E. Alwan and A. Madanayake, "Design of 28 GHz 64-QAM Digital Receiver," 2019 International Workshop on Antenna Technology (iWAT), 2019, pp. 193-196, doi: 10.1109/IWAT.2019.8730596.
- A passive STAR microwave circuit for 1-3 GHz self-interference cancellation U. D. Silva, S. Pulipati, S. B. Venkatakrishnan, S. Bhardwaj and A. Madanayake, "A Passive STAR Microwave Circuit for 1-3 GHz Self-Interference Cancellation," 2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, pp. 105-108, doi: 10.1109/MWSCAS48704.2020.9184595.
- RF-Rate Hybrid CNN Accelerator Based on Analog-CMOS and Xilinx RFSoC U. De Silva, S. Mandal, A. Madanayake, J. Wei-Kocsis and L. Belostotski, "RF-Rate Hybrid CNN Accelerator Based on Analog-CMOS and Xilinx RFSoC," 2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, pp. 1-5, doi: 10.1109/ISCAS45731.2020.9180556.
- Implementation and testing of a switching circulator for twin-pair STAR radio architectures U. De Silva, H. Malavipathirana, S. Pulipati, S. Bhardwaj, S. Mandal and A. Madanayake, "Implementation and Testing of a Switching Circulator for Twin-Pair STAR Radio Architectures," 2020 Moratuwa Engineering Research Conference (MERCon), 2020, pp. 331-336, doi: 10.1109/MERCon50084.2020.9185263.
- IEEE 802.3 100Gbps Ethernet PCS IP design challenges and solutions U. P. De Silva, A. Lokumarambage, H. Malavipathirana, C. Mohottala and S. Thayaparan, "IEEE 802.3 100Gbps Ethernet PCS IP design challenges and solutions," 2016 IEEE Symposium on Computer Applications & Industrial Electronics (ISCAIE), 2016, pp. 21-25, doi: 10.1109/ISCAIE.2016.7575030.
- A Modular 1D-CNN Architecture for Real-time Digital Pre-distortion Udara De Silva (1), Toshiaki Koike-Akino (1), Rui Ma (1), Ao Yamashita (2), Hideyuki Nakamizo (2) ((1) Mitsubishi Electric Research Labs, Cambridge, MA, USA, (2) Mitsubishi Electric Corporation, Information Tech. R&D Center, Kanagawa, Japan)
- A Comparison of AI-Enabled Digital Twins for DSP-based Self-Interference Cancellation in Wideband Full-Duplex Communications U. De Silva et al., "A Comparison of AI-Enabled Digital Twins for DSP-based Self-Interference Cancellation in Wideband Full-Duplex Communications," 2021 IEEE-APS Topical Conference on Antennas and Propagation in Wireless Communications (APWC), 2021, pp. 136-136, doi: 10.1109/APWC52648.2021.9539817.